Sub-1nm Process Technology Won’t Arrive Till 2034, Logic Roadmap Highlights 2D FETs For 0.2nm & Sub 0.2nm Nodes By 2043-2046

May 2, 2026 - 18:58

The semiconductor industry is mapping out a long and winding road to the next frontier of miniaturization. According to the latest logic technology roadmap, the arrival of sub-1nm process technology is now expected around the year 2034. This timeline reflects the growing difficulty of shrinking transistors further as traditional silicon approaches its physical limits.

The roadmap outlines a gradual transition away from conventional fin field-effect transistors (FinFETs) toward more advanced architectures. For the 0.2nm node and beyond, the industry is betting on two-dimensional field-effect transistors (2D FETs). These devices use atomically thin materials, such as molybdenum disulfide, to maintain control over the transistor channel at extreme scales.

The projected timeline for 2D FETs entering commercial production stretches from 2043 to 2046. This suggests that the industry expects a decade-long gap between the first sub-1nm nodes and the adoption of truly novel transistor designs. The delay is partly due to the immense challenges in manufacturing, including defect control and integration with existing chip fabrication processes.

While Moore's Law has clearly slowed, the roadmap shows that logic scaling is far from dead. Instead, progress is becoming more incremental and reliant on new materials and device structures rather than simple lithographic shrinks. Chipmakers will need to solve fundamental physics and engineering problems to keep performance and power efficiency improving into the 2040s.